1. Field of the Invention
The present invention relates to an audio signal processing apparatus which enables transmission and reception of audio signals through a bus for transmitting audio signals among a plurality of nodes connected to the bus.
2. Description of the Related Art
An example of a conventional musical tone synthesizer is shown in FIG. 17 as well as shown in Japanese Patent Laid-Open No. 2004-102131, the musical tone synthesizer allowing transmission and reception of audio signals through a bus for transmitting audio signals among a plurality of nodes connected to the bus.
In the musical tone synthesizer shown in FIG. 17, a MIDI I/O (Input/Output) portion 202 inputs and outputs MIDI signals between an external MIDI apparatus. Through the MIDI I/O portion 202, more specifically, MIDI performance information transmitted from a MIDI keyboard or a MIDI performance operator, for example, is input to the musical tone synthesizer. An additional I/O (Input/Output) portion 204 inputs and outputs various kinds of signals other than MIDI signals. A panel switch portion 206 includes various kinds of tone color setting operators manipulated by a user. A tone generator 250, which includes tone generator LSI circuits 252, 254, synthesizes musical tone signals. A display unit 208 displays various kinds of information such as settings of the tone generator 250 for the user. An external storage device 210 is configured by a hard disk and the like. A CPU 212 executes control programs to control various portions of the musical tone synthesizer through a CPU bus 218. A ROM 214 stores the control programs executed by the CPU 212. A RAM 216 is used as a working memory of the CPU 212.
The tone generator LSI circuits 252, 254 which configure the tone generator 250 generate waveform data on the basis of performance information, parameters for emitting tones and the like, the performance information and parameters being supplied through the CPU bus 218. The tone generator LSI circuits 252, 254 also add various kinds of effects to the waveform data on the basis of similarly supplied effect parameters and the like. Add-on boards 256, 258, 260 of the tone generator 250, which carry out various kinds of processing such as synthesizing waveform data, adding effects, and keeping logs according to the type of the add-on boards, help the tone generator 250 achieve certain functions along with the tone generator LSI circuits 252, 254. A bus for transmitting waveform data (hereinafter referred to as “A bus”) 262 is a bus which allows transmission of waveform data among the tone generator LSI circuits 252, 254 and the add-on boards 256, 258, 260. The A bus 262 allows transmission of only waveform data having no information on destination address and the like, broadening the transmission band of waveform data.
Because the amount of waveform data transmitted between the tone generator LSI circuits 252, 254 is large, part of the waveform data is transmitted through a line which directly connects the tone generator LSI circuit 252 with the tone generator LSI circuit 254. A DA converter 264 converts waveform data of two channels of output channels of the tone generator LSI circuit 252 into analog signals to emit tones from a sound system 220 on the basis of the converted analog signals for two channels. A word clock generator 251 generates word clock WCK which is pulled up at each sampling cycle. The word clock WCK is supplied to the respective portions of the tone generator 250. A word clock external input terminal 268 is a terminal provided in order to receive externally provided word clock WCK instead of the word clock WCK generated by the word clock generator 251. The word clock external input terminal 268 is used in a case where the tone generator 250 synchronizes the sampling cycle with that of an external apparatus. The add-on boards 256, 258, 260 are detachable from the tone generator 250.
The tone generator LSI circuits 252, 254 and the add-on boards 256, 258, 260 which input/output waveform data via the A bus 262 configure nodes, which are node A, node B and node C. To/from the respective nodes, a data signal ADAT, a direction signals ADIR and a clock signal ACLK are input/output to/from the A bus 262. These nodes are wired-OR connected to the A bus 262 to input/output these signals. While any node outputs a signal to the A bus 262, the input/output terminals of the other nodes are set at high impedance to receive signals transmitted through the A bus 262 as needed. The data signal ADAT is a signal such as waveform data to be transmitted between the nodes, while the clock signal ACLK is a clock signal which synchronizes with the data signal ADAT.
Periods during which the data signal ADAT and the clock signal ACLK are to be output are determined by the CPU 212 so as to avoid overlap among the nodes. The period is referred to as “frame”. During the frame period, the direction signal ADIR is set at “L” to prohibit the other nodes from outputting signals. The respective nodes also output a frame signal AFRM pulled up a clock of the clock signal ACLK earlier than pulling up to “H” of the direction signal ADIR. Each frame assigned to each node is defined on the basis of the ordinal position of the frame counted from pulling up of a word clock WCK. Therefore, each of the nodes detects a timing at which a frame of the node starts by counting the number of generated frames since the pulling up of a word clock WCK.
FIG. 18 shows a diagram indicative of timings of a case where node A is assigned frame #2 which is the third frame as a transmission frame, node B is assigned frame #0 which is the first frame, and node C is assigned frame #1 which is the second frame. At time t0 shown in FIG. 18, the word clock WCK is pulled up. The pulling up of the word clock WCK is detected by the respective nodes A, B and C. Node B to which frame #0 is assigned pulls down a direction signal ADIR and a frame signal AFRM to “L” at time t1 when a certain time period has passed since time t0 to output a clock signal ACLK and a data signal ADAT which synchronizes with the clock signal ACLK.
At time t2 when the output of data from node B is completed, the direction signal ADIR of node B is pulled up to “H”. Due to pulling up of the frame signal AFRM to “H” a cycle of clock signal ACLK earlier than time t2, node C recognizes that the next frame is frame #1 which is assigned to node C. At time t3 when a certain margin time has elapsed after pulling up of the direction signal ADIR, node C operates similarly to the above description about node B. More specifically, node C pulls down the direction signal ADIR and the frame signal AFRM of node C to “L” to output the clock signal ACLK, and also outputs the data signal ADAT in synchronization with the clock signal ACLK. The margin times between frames are provided in order to prevent collision of data. If the frame signal AFRM of node C is pulled up to “H”, node A determines that the next frame is frame #2 which is assigned to node A. After the direction signal ADIR of node C has been pulled up to “H” at time t4, node A executes output processing similar to that described above at time t5 when the certain margin time has elapsed.